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> Smaller, faster, cooler : The Chips race !
Old Bear
post Jan 27 2007, 12:30
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I have read in the New York Times a new about Intel’s imminent advance to 45 nanometers.

QUOTE
Intel said it had already manufactured prototype microprocessor chips in the new 45-nanometer process that run on three major operating systems: Windows, Mac OS X and Linux.


It's an incredible issue, it says that Moore’s Law is still workin' !


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D@V£
post Jan 27 2007, 14:26
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Weren't they transistors on the chips that were 45nM? Not the chips themselves?


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post Jan 30 2007, 12:03
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QUOTE(D@V£ @ Jan 27 2007, 14:26) *

Weren't they transistors on the chips that were 45nM? Not the chips themselves?


Yeah Im pretty sure that the transistors on the chips were 45nM, but then again I only read briefly into it. But I got the feeling that the 45nM was the transistors and not the actual chip itself.


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Blackscorpion
post Jan 31 2007, 13:01
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Processor the size of 45 nm would bring some installing problems to most people tongue.gif... bear in mind, nanometer is one millionth of millimeter.


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Old Bear
post Sep 21 2007, 10:10
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IDF: Moore gives his law 10-15 years :

Chip researchers will hit fundamental physical limits in the next 10 to 15 years that will prevent them from further shrinking chip sizes, Intel co-founder Gordon Moore predicted at the Intel Developer Forum.

Moore is best known for a theory published in 1965, predicting that transistor sizes will decrease by 50 per cent every 18 to 24 months.

As a result, chip speeds will double or prices will be cut in half. The theory has become known as Moore's Law.

QUOTE
"In another decade, decade and half, we will hit something that is fundamental," Moore said when asked if there would be an end to his 'law'.

But he also pointed out that there have always been fundamental barriers that prevent chip technologies from further advancing.

QUOTE
"There really are some fundamental limits, but it has been amazing to me how the technologies have been able to keep pushing those out,"

"As long as I can remember, the fundamental limits are two, three generations out. So far we have been able to get around them."

Intel has been pushing the development of 45nm processors, for example. Current 65nm chips use gate materials that are only five molecules thick. Any further decrease would have caused a drastic increase in power leakage.

But the chip giant started to use hafnium to build smaller, more efficient transistors.

Source : vnunet.com

32-nm chip technology announced

Intel Corp. said Tuesday it will ramp up performance and energy efficiency in its microprocessors by using a 32-nanometer process technology starting in 2009.

Intel isn't the first to announce 32-nm chip technology. In May, a group of chip makers led by IBM Corp. agreed to further collaborate to jointly develop 32-nm semiconductor production technology. Other companies in the collaboration include Freescale Semiconductor Inc., Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG and Samsung Electronics Co. Ltd.

Source : PCWorld


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UNIT-716
post Nov 2 2007, 22:37
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Iv read alot on the shrinking of processor dies and frankly im amazed that we have 45nm chips now considering the inherent problems due to the phisical limits of silicone... I dont know what Intel is using for their chips but ill go with old bears reserch on this one. plus the chips proberly use quantum wells to increse the efficiency of the data pathways.

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QUOTE(D@V£ @ Jan 27 2007, 13:26) *
Weren't they transistors on the chips that were 45nM? Not the chips themselves?


acttualy the 45nm doesnt refer to the lowly teransistor but the gap between them. As electrical components get closer together (50nm and smaller I think) an effect called quantum tunneling ocures where the blocked electron streams try to unblock themselvs by conecting with other electron streams around them, they tunnel through the dielectric material and short-circuit << proberly the shortest version of that story around, if you want to know more wiki or google it.


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D@V£
post Nov 3 2007, 01:23
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Ugh, please, for the love of god, don't bring quantum mechanics into it.

The quantum level effects won't happen on this scale. Quantum Tunnel relys on a Square Well Potential, if you've got that on a transister you're;
A. The worlds greatest genius for making a device with a square well potential at 50nm
B. The worlds greatest idiot for managing to screw up a transistor at a quantum level

Andyways*, simpley put, you can't measure the "gap" in the transitor, it changes size depending on the potential across said transistor.






*I typed it out like that... I don't know why, I couldn't bring myself to correct it


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Old Bear
post Nov 12 2007, 20:27
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Intel has released it's new 45 nm multicore CPUs, one Intel Core 2 Extreme QX9650 quad core processor and 15 quad core Intel Xeon.


QUOTE
SANTA CLARA, Calif., Nov. 11, 2007 – Built using an entirely new transistor formula that alleviates the wasteful electricity leaks that threaten the pace of future computer innovation, Intel Corporation today unveiled 16 server and high-end PC processors. In addition to increasing computer performance and saving energy use, these processors also eliminate eco-unfriendly lead and, in 2008, halogen materials.

Called the biggest transistor advancements in 40 years by Intel Co-Founder Gordon Moore, the processors are the first to use Intel's Hafnium-based high-k metal gate (Hi-k) formula for the hundreds of millions of transistors inside these processors. These Intel® Core™ 2 Extreme and Xeon® processors are also the first to be manufactured on the company's 45-nanometer (nm) manufacturing process, further boosting performance and lowering power consumption.
...
The Intel Core 2 Extreme QX9650 quad core processor, the world's first 45nm Hi-k desktop processor, delivers more of the adrenaline that hardcore gamers and media enthusiasts demand. Enhancements such as a larger L2 cache and support for new Intel® SSE4 media instructions help bring desktop performance to "extreme" new levels.
...
Pricing of the 45nm Hi-k Intel Xeon processors depends on the model, speeds, features and amount ordered, and ranges from $177 to $1,279 in quantities of 1,000. The 45nm Hi-k Intel Core 2 Extreme QX9650 quad core processor is priced at $999 in quantities of 1,000. Depending on the model, these processors are available today or within 45 days.



Source : Intel web site



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Old Bear
post Jul 8 2008, 18:15
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Thanks to Gizmodo web site, we had an idea of Pat Gelsinger, the Intel’s Chief Technology Officer, prediction about future chips:

QUOTE
Think Intel's breakthrough 45-nanometer chips are impressive stuff? Intel thought at one time dipping below 100nm would be miraculous, but Intel exec Pat Gelsinger says that "today we see a clear way to get to under 10 nanometers," and it'll be within the next 10 years.

The next die shrink is the 32nm Westmere chips next year, followed by 14nm a few years later and then the crazy sub-10nm chips after that. But they're probably going to have to make use of something like carbon nanotubes or spintronics to get below 10. The result of all that processing power, says Gelsinger, will be "a dramatic restructuring of the user interface."

I do like the "clear way" concept knowing nobody has any practical idea of how it can be attainable, speaking of "carbon nanotubes or spintronics" is just SciFi at the moment

Of course, as was stating Expreview site :

QUOTE
Since 1965 Moore first introduced his law, semicondutor industry drived through 33 years with a tremedous speed, from 10μm in 1971 to 3μm in 1978, from 1μm in 1989 to 0.25μm in 1997, to 65nm in 2005. Thirty years proves Moore’s law is right. Although they came into frustration by the end of Pentium 4, the bootleneck of heat-spread was broken finally. Now, let’s pay attention to Intel, to the Moore’s law.

But Moore himself was dubious about his so-called law because of limits at the molecular then atomic level.


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Old Bear
post Dec 12 2008, 17:28
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Still on the move Intel has announced that they have "... completed the development phase of its next-generation manufacturing process that will be used to make 32nm chips, and said it is on track for production in the fourth quarter of 2009.

Read here full new from vnunet.com, Intel: 32nm process is ready to go



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Old Bear
post Aug 31 2010, 14:45
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Here is a new I have been awaiting ... because, I am still still wondering about Moore's Law ... from The New York Times,
QUOTE
Advances Offer Path to Shrink Computer Chips Again

In one of the two new developments, Rice researchers are reporting in Nano Letters, a journal of the American Chemical Society, that they have succeeded in building reliable small digital switches — an essential part of computer memory — that could shrink to a significantly smaller scale than is possible using conventional methods.

More important, the advance is based on silicon oxide, one of the basic building blocks of today’s chip industry, thus easing a move toward commercialization. The scientists said that PrivaTran, a Texas startup company, has made experimental chips using the technique that can store and retrieve information.

These chips store only 1,000 bits of data, but if the new technology fulfills the promise its inventors see, single chips that store as much as today’s highest capacity disk drives could be possible in five years. The new method involves filaments as thin as five nanometers in width — thinner than what the industry hopes to achieve by the end of the decade using standard techniques. The initial discovery was made by Jun Yao, a graduate researcher at Rice. Mr. Yao said he stumbled on the switch by accident.

Separately, H.P. is to announce on Tuesday that it will enter into a commercial partnership with a major semiconductor company to produce a related technology that also has the potential of pushing computer data storage to astronomical densities in the next decade. H.P. and the Rice scientists are making what are called memristors, or memory resistors, switches that retain information without a source of power.

“There are a lot of new technologies pawing for attention,” said Richard Doherty, president of the Envisioneering Group, a consumer electronics market research company in Seaford, N.Y. “When you get down to these scales, you’re talking about the ability to store hundreds of movies on a single chip.”

The announcements are significant in part because they indicate that the chip industry may find a way to preserve the validity of Moore’s Law. Formulated in 1965 by Gordon Moore, a co-founder of Intel, the law is an observation that the industry has the ability to roughly double the number of transistors that can be printed on a wafer of silicon every 18 months.


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Old Bear
post Feb 21 2011, 16:34
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Two announcements from the chips builders front :

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Intel CEO Paul Otellini announced his intentions to build the fab during a visit of President Barack Obama at Intel’s Hillsboro, Oregon, site last Friday. The new factory will be called Fab 42 is expected to be completed in 2013 and mass-produce semiconductors in a 14 nm process. Intel is expected to launch 22 nm processors by the end of this year and introduce 14 nm chips in 2013.

“The investment positions our manufacturing network for future growth,” said Brian Krzanich, senior vice president and general manager, Manufacturing and Supply Chain. “This fab will begin operations on a process that will allow us to create transistors with a minimum feature size of 14 nanometers. For Intel, manufacturing serves as the underpinning for our business and allows us to provide customers and consumers with leading-edge products in high volume. The unmatched scope and scale of our investments in manufacturing help Intel maintain industry leadership and drives innovation.”


Source : ConceivablyTech.com

QUOTE
The consortium members-ARM, Globalfoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—have announced results of an assessment and characterization of FD-SOI, saying that the technology is viable for mobile and consumer devices at the 20-nm node and perhaps beyond. The group has demonstrated the benefits of planar FD-SOI technology for these applications based on an ARM processor.
FD-SOI is one of several options competing for the next-generation transistor structure. At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the 32-/28-nm nodes.

AMD, IBM and others are also using another type of SOI technology-partially depleted SOI-for their respective processors. In contrast, Intel Corp. has dismissed SOI, saying that it does not require the technology.

For 22- and 16-nm, there are a number of transistor candidates on the table: III-V, bulk CMOS, FinFET, FD-SOI, multi-gate, among others. So far, there are no clear winners.

Mark Bohr, Intel Senior Fellow and director of process architecture and integration at Intel Corp., recently said the chip giant is evaluating extremely-thin SOI, sometimes called FD-SOI. One source even thinks Intel is looking at rival tri-gate structures at 22- or at 15-nm. Bohr declined to elaborate on Intel’s directions.

In a recent interview, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM Corp., said FD-SOI is a strong candidate for the 22-nm node. Some of the big silicon foundries-Globalfoundries, Samsung and TSMC-have dropped hints that they will push bulk CMOS silicon for the 20-nm node due to cost.

But many high-performance applications may also require FD-SOI. SOI refers to the use of a layered silicon-insulator-silicon substrate in IC manufacturing, which is said to reduce parasitic device capacitance and improve performance.

In FD-SOI, the top silicon layer is between 5- to 20-nm thick. ''Silicon under the gate is so thin that it is fully depleted of mobile charges,’’ according to Soitec, in a newsletter. ''There is no floating body effect.’’

In partially depleted SOI, the top layer is between 50- to 90-nm thick. Silicon under the channel is partially depleted of mobile charge. This in turn can ''lead to charges accumulating in the quasi-neutral region,’’ which can cause the floating-body affect.

One of the issues for SOI is whether it’s suited for the mobile market; there are concerns about the scalability and so-called ''history effect.’’ For years, SOI has been used in desktop processors and other high-performance applications.

Now, the SOI crowd is pushing the technology for mobile applicatons. At last year’s Semicon West trade show, SOI substrate specialist Soitec Group (Paris) said the company was readying its Ultra-Thin Buried Oxide (UTBOX) extension to its Ultra-Thin (UT) silicon-on-insulator (SOI) platform-or FD-SOI-for mobile consumer devices.

With ultra-thin top silicon thickness variation within a +/- 0.5nm maximum range, and a buried oxide layer as thin as 10-nm, these wafers are in full compliance with customer requirements, according to Soitec. High-volume capacity has been available for the 22-nm node at Soitec's manufacturing sites in France and Singapore.

In 2008, IBM Corp.'s Microelectronics Group rolled out what it claims is the industry's first 45-nm, silicon-on-insulator (SOI) foundry offering. It's unclear if IBM will offer the same service for FD-SOI.

Meanwhile, it’s possible that Soitec jumped the gun on last year's announcement at Semicon. It’s still unclear if chip makers will jump on FD-SOI or not for the next nodes. Perhaps chip makers remain worried about the design considerations in the mobile space.

Now, the SOI Consortium is throwing its weight behind FD-SOI for mobile. “FD-SOI is a great option to improve the key metrics for mobile markets: power, frequency, manufacturability and most importantly cost efficiency,” said Horacio Mendez, executive director of the SOI Industry Consortium. FD-SOI is scalable, fully compatible with bulk silicon and can be manufactured with no ''history effect,’’ he added.

Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40 percent while maintaining the stability of the SRAM, according to the consortium.

Traditionally, low power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20 percent to 30 percent. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80 percent gain can be achieved beyond the traditional increase, according to the group.

Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost efficient approach to further shrinking CMOS transistors, according to the group.


Source : EETimes Europe

About Multigate device on Wikipedia


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Old Bear
post Dec 5 2011, 18:46
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Pat Bliemer from Intel : "14nm running in the lab"

QUOTE
Intel already has 14nm circuits up and running in the lab, this was revealed by Pat Bliemer, Managing Director Intel Northern Europe, in an interview with NordicHardware. Bliemer says that even though the manufacturing technology is becoming all the more complicated Intel is well in phase with current roadmaps.

Intel was the first semiconductor manufacturer to use 32 nanometer technology for mass production of microprocessors and next year by the end of the first quarter it will roll out the Ivy Bridge architecture with a brand new 22 nanometer process sporting so called 3D transistors, also known as Tri-gate transistors. During an interview with NordicHardware at DreamHack Winter 2011, Managing Director Intel Northern Europe, Pat Bliemer pointed out that with the launch of Ivy Bridge Intel will be one and a half node ahead of the competition

Full new on www.nordichardware.com


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